As production geometries of processor systems with their associated memories decrease, the opportunities for defects in the finished products increase. These defects, along with other physical events (e.g., cosmic ray passage), can result in increasing bit error rates in system memories. Along with increasing single bit error rates are the increasing probability of double bit errors in a given area of memory.
Today's high density memories can be subject to increased incidents of bit errors than lower density memories. Process technologies used to manufacture high density memories can result in defects that cause persistent weak bits. Further, multiple neighboring bits can be subject to these defects due to processing. In addition, transient bit errors can affect multiple neighboring bits in high-density memories.
Single bit error correction methods have been used to correct occurrences of errors in a single bit of an area of memory. Single bit error correction methods, such as Hamming code methods, are attractive because they can be performed in a manner that has a minimal impact on memory latency (e.g., in a single clock cycle). But single bit error correction methods cannot correct both a transient bit error and a persistent weak bit error occurring in the same area of memory. In a circumstance where a region of memory has a double bit (or higher) error, and only single bit error correction is used, that region of memory will require reloading from a data source to correct the error. Such reloading increases memory latency due to cycles spent requesting, reading, and loading the data from the source to the region of memory.
To resolve issues related to double bit errors, polynomial code based error correction methods, such as Bose-Chaudhuri-Hocquenghem (BCH) code, can be used. These double bit error correction methods have an advantage over single bit error correction methods in that they can significantly improve memory reliability. For example, double bit error correction methods can correct both a transient bit error and a persistent weak bit error in a same area of memory. While double bit error correction methods are robust, the process of determining the location of the errors and correcting the errors are non-trivial and can result in significantly longer memory latencies than those found in single bit error correction methods. Thus, traditionally, a tradeoff has been required between memory latency and memory reliability through correction of higher numbers of bit errors.
Each word or entry in non-volatile memory has a fixed number of bits that includes a data portion and a number of spare bits for parity data. As flash memory is reprogrammed over a number of cycles, correction of higher numbers of bit errors requires more correction capability with a corresponding increase in the number of parity bits. If the number of bits allocated for parity increases, the number of bits available for storing data is reduced.
As the size of flash memory 106 grows, the size of each page in flash memory 106 can also increase. Meanwhile, sector size stays relatively fixed (either 512 Byte or 4 K Byte). In order to support the more efficient ECC of the larger pages, sectors cannot be written without updating the page ECC information. NAND flash memory 106 requires erase before programming so the sector writes cause increased wear of the bit cells due to the need to access all of the cells on the page to update the ECC information.